1. Field of the Invention
The present invention relates to a power semiconductor integrated circuit device, and more particularly, to a power semiconductor integrated circuit device which is less affected by a voltage applied to a wiring layer.
2. Description of the Related Art
Lateral semiconductor devices such as FRDs (Fast Recovery Diode), power bipolar transistors, power MOS transistors, and IGBTs, to which a high voltage is applied, have been used in a power semiconductor integrated circuit device including a three-phase full bridge circuit, a rectifying circuit, a switching regulator, a high-side switching circuit, and a low-side switching circuit. In the power semiconductor integrated circuit device, a potential difference between two diffused layers can rise to several hundreds volts or more upon the application of a high voltage.
FIG. 8 shows an example where a voltage is applied across the two diffused layers. An N.sup.+ -type diffused layer 102 and a P.sup.+ -type diffused layer 103 are formed in an N.sup.- -type semiconductor substrate 101 to provide a lateral diode. An insulating film 104 is formed on the substrate surface, and first and second wiring layers 105 and 106 are provided on the diffused layers 102 and 103, respectively. In this case, when a voltage is applied such that the first diffused layer 102 is provided with high voltage with respect to the second diffused layer 103, an electric field of the substrate 101 between the diffused layers 102 and 103 is uniformly distributed, thereby providing equipotential lines 107 (dotted line) having equal intervals. In this case, a breakdown voltage is determined by a point exceeding the critical potential density (avalanche breakdown) of silicon.
However, since a large number of wiring layers are required for the power semiconductor integrated circuit device, a portion of them must pass through semiconductor regions having different potentials. FIG. 9A shows a case where the first wiring layer 105 extending from the first diffused layer 102 passes over the second diffused layer 103 having a potential difference of about several hundreds volts or more. When a reverse bias voltage is applied between the first and second diffused layers 102 and 103, the electric field is concentrated at a portion surrounded by a circle (electric field concentration portion 108) where the second diffused layer 103 is crossed by the first wiring layer 105, as indicated by the equipotential lines 107. As shown in FIG. 9B, the potential of the semiconductor substrate 101 is abruptly changed near the second diffused layer 103, i.e., at a portion where the electric field is concentrated. When the electric field concentration density exceeds a critical point of the breakdown voltage of the semiconductor substrate 101, breakdown occurs due to the concentration of the electric field. Therefore, a desired breakdown voltage cannot be obtained.
Referring to FIG. 10, there will be described a semiconductor device that includes a P.sup.+ -type diffused layer 122 and an N.sup.+ -type diffused layer 123 formed in an N.sup.- -type semiconductor substrate 121, an insulating film 124 formed on the substrate surface, and a wiring layer 125 extending from the first diffused layer 122 and passing over the second diffused layer 123. A voltage is applied to the semiconductor device such that a potential difference between the first and second diffused layers 122 and 123 is several hundreds volts or more and the first diffused layer 122 has a low voltage with respect to the second diffused layer 123. In this case, equipotential lines 107 are concentrated to the N.sup.- -N.sup.+ interface (a portion indicated by a circle 108), thereby causing the breakdown.
At any rate, as shown in FIGS. 9A and 10, when a wiring layer passes over a diffused layer having a different potential, an electric field is concentrated at a portion of the device thereby reducing the breakdown voltage. For this reason, the following techniques have been proposed for increasing the breakdown voltage.
One of the techniques is that thickness of the insulating film 104 under the wiring layer 105 is increased as shown in FIG. 11. The electric field in the insulating film 104 is then easily relieved to reduce the concentration of the electric field in the semiconductor substrate 101. This technique can be applied to the process steps in making the semiconductor device without using new materials. However, the lateral type high breakdown voltage devices are generally used for integrated circuits, and are often provided in the same semiconductor substrate together with signal processing circuits having a low breakdown voltage and a small size. As shown in FIG. 11, if the insulating layer is thick, a contact hole formed in the insulating layer must be tapered. Therefore, a margin for taper processing is required in proportion to the thickness of the insulating layer. Consequently, the increase in thickness of the insulating layer will increase, e.g., the size of the signal processing circuits, thereby reducing the integration density of the overall integrated circuit device.
Another technique will be described below with reference to FIG. 12. A resistor, formed of semi-insulating polysilicon (to be referred to as SIPOS hereinafter) 109, having a high resistance, is formed in the insulating film 104 under the wiring layer 105. Opposite ends of the SIPOS 109 are connected to the first and second diffused layers 102 and 103, respectively, and are maintained at the electric potential thereof. The SIPOS 109 is a resistor having a high resistance, and the electric potential is uniformly distributed by the potential difference between both ends of the SIPOS 109. As indicated by the equipotential lines 107, the electric field is almost uniformly distributed in the semiconductor substrate 101 under the SIPOS 109. Therefore, the breakdown voltage can be increased to be approximately equal to the ideal breakdown voltage of the substrate. However, since the semi-insulating polysilicon is not normally used for the semiconductor device, the number of process steps is increased which therefore will increase the cost.
Still another technique will be described below with reference to FIGS. 13A and 13B. As shown in FIG. 13A, floating potential polysilicon layers 110 are fragmentarily arranged in the insulating film 104 under the wiring layer 105. As shown in FIG. 13B, the floating potential polysilicon layers 110 are arranged in parallel in the form of strips under the wiring layer 105. Each of the floating potential polysilicon layers 110 serves as a field plate, and the potential of each of the floating potential polysilicon layers 110 is fixed to a predetermined potential due to the influence of a leakage electric field from the semiconductor substrate 101. Therefore, the electric field is not concentrated and is uniformly distributed under the floating potential polysilicon layers 110, thereby obtaining an electric field distribution indicated by equipotential lines 107 in FIG. 13A.
According to the above technique, the cost is not increased because the integration density is not decreased and new materials are not used. However, the potential of each of the field plates is affected by the arrangement and shape of the field plates, the impurity concentration of the semiconductor substrate, the applied voltage, and the like. For this reason, the field plates must be optimally designed by using a computer in advance. A satisfactory effect therefore cannot be obtained without an optimal design. Even if the field plates are optimally designed at a certain potential, the potential variation makes it very difficult to perform the optimal design under all the conditions. Therefore, difficulties in the design of the field plates exist.
As described above, when a high-voltage wiring layer passes over a diffused layer having a potential difference of several hundreds volts or more, an electric field is concentrated to cause a breakdown. Therefore, a predetermined breakdown voltage cannot be obtained.